A cell transistor in a conventional NAND flash memory includes a tunneling insulator, a floating gate, an IPD (Inter Poly-Si Dielectric) film, and a control gate which are stacked in this order on an active area of a substrate. In general, the active area, the tunneling insulator, the floating gate, the IPD film, and the control gate are respectively formed of p−-silicon, silicon oxide, n+-polysilicon, silicon oxynitride, and n+-polysilicon.
When the cell transistor is miniaturized, a short channel effect and adjacent cell interference can be effectively restrained by thinning the tunneling insulator. However, if the cell transistor is miniaturized so that the tunneling insulator is thinned to achieve a gate length shorter than 20 nm, an electric field applied to the tunneling insulator becomes extremely large when charges are retained in the floating gate. When a large electric field is applied to the tunneling insulator, the charges in the floating gate escape as a tunneling current into the substrate. In this manner, the miniaturization of the cell transistor results in degradation of charge retention characteristics of the cell transistor.
The cell transistor is expected to have not only excellent charge retention characteristics but also a high writing speed and a high erasing speed. However, if n+-doping is insufficient in the floating gate of n+-polysilicon, the lower portion of the floating gate is depleted at the time of writing. With such depletion, a tunneling current as a write current cannot flow easily, and the writing speed becomes lower.